This invention relates to semiconductor integrated circuits and, more particularly, to a resistor mirror. A resistor mirror is defined herein as a circuit which measures the resistance of an input device and, based on that measurement, induces one or more output devices to each exhibit a substantially similar resistance (or, through fixed or programmable scaling, a multiple or fraction of the resistance of the first device). This resistive output device is particularly suited for use within an integrated circuit as a transmission line termination, an amplifier load, or the resistive component in a filter. Its scalability, programmability, and ability to track a stable, external reference resistor in the presence of temperature and process variation make this resistor mirror particularly versatile. FIG. 1 is a schematic diagram illustrating a resistor mirror 99 of the prior art. Resistor mirror 99 includes successive approximation register (SAR) 30, feedback control circuit 14, reference voltage-controlled resistor 15, and a second voltage-controlled resistor 16 coupled to resistor mirror output ROUT.
SAR 30 is coupled to input terminals RESET and CLK, internal node CONTROL, and resistor control output terminals RBIAS1, RBIAS2, and RBIAS3. Feedback control circuit 14 includes a control input terminal coupled to feedback node FB and a control output terminal coupled to CONTROL. Feedback control circuit 14 further includes reference resistor R1 coupled between supply terminal VDD and internal reference node INTREF; differential to single-ended amplifier U1 having a non-inverting input coupled to INTREF, an inverting input coupled to external reference voltage input REF, and an output coupled to bias node BIAS; n-channel transistor M7 having a drain coupled to INTREF, a gate coupled to BIAS, and a source coupled to supply terminal VSS; n-channel transistor M8 having a drain coupled to FB, a gate coupled to BIAS, and a source coupled to VSS; and comparator U2 having an inverting input coupled to INTREF, a non-inverting input coupled to FB, and an output coupled to CONTROL. In one embodiment, external reference voltage input REF is a constant voltage substantially equal to the expected minimum voltage at ROUT. Differential to single-ended amplifier U1 of FIG. 1 is used to bias transistors M7 and M8 such that each conducts a current substantially equal to (VDDxe2x88x92VREF)/RR1.
Reference voltage-controlled resistor 15 includes p-channel transistor M1 with a drain coupled to FB, a source coupled to VDD, and a gate coupled to RBIAS1; p-channel transistor M2 with a drain coupled to FB, a source coupled to VDD, and a gate coupled to RBIAS2; and p-channel transistor M3 with a drain coupled to FB, a source coupled to VDD, and a gate coupled to RBIAS3.
A second voltage-controlled resistor 16 includes p-channel transistor M4 with a drain coupled to ROUT, a source coupled to VDD, and a gate coupled to RBIAS1; p-channel transistor M5 with a drain coupled to ROUT, a source coupled to VDD, and a gate coupled to RBIAS2; and p-channel transistor M6 with a drain coupled to ROUT, a source coupled to VDD, and a gate coupled to RBIAS3.
FIG. 2 shows operation of resistor mirror 99 of FIG. 1 using SAR 30 and an adjustment sequence to determine optimum logic levels for RBLASn (n=1,2,3) so as to most closely match the resistance of reference voltage-controlled resistor 15 to the resistance of R1. Controlled by RESET and CLK, SAR 30 is used to successively set or clear (assert to a logic high or logic low level) RBIASn (n=1,2,3), depending on the CONTROL logic level. The relative resistance of the voltage-controlled resistor 15 and of R1 is determined by conducting substantially equal currents through each (by means of equal-sized and similarly-biased n-channel transistors M7 and M8) and comparing the resulting voltages INTREF and FB using comparator U2. At time 0 in FIG. 2, RESET is asserted high, SAR 30 resets RBIAS1 low and also sets RBIAS2 and RBIAS3 high, and in response VFB greater than VINTREF, and feedback control circuit 14 forces CONTROL to a logic high level, indicating that the resistance of reference voltage-controlled resistor 15 is less than that of reference resistor R1.
On the first rising edge of CLK subsequent to the falling edge of RESET, SAR 30 resets RBIAS2 to a logic low level, and the logic high level on CONTROL causes SAR 30 to also set RBIAS1 to a logic high level. In response to this change in RBIASn (n=1,2,3) levels, now VFB less than VINTREF, and CONTROL falls to a logic low level, indicating that the resistance of reference voltage-controlled resistor 15 is now greater than that of resistor resistor R1.
On the second rising edge of CLK subsequent to the falling edge of RESET, SAR 30 resets RBIAS3 to a logic low level, and the logic low level on CONTROL causes SAR 30 to also keep RBIAS2 at a logic low level. In response to these RBLASn (n=1,2,3) levels, CONTROL remains at a logic low level, indicating that the resistance of reference voltage-controlled resistor 15 remains greater than that of reference resistor R1.
On the third rising edge of CLK subsequent to the falling edge of RESET, the logic low level on CONTROL causes SAR 30 to keep RBIAS3 at a logic low level. At this point, the resistance of reference voltage-controlled resistor 15, and by extension, the resistance of the second voltage-controlled resistor 16, has been adjusted to approximately match that of R1.
This prior art resistor mirror has several significant drawbacks. First, because digital logic levels are used to control each p-channel transistor making up the voltage-controlled resistors, there is no way to partially turn on the transistors. This digital method of controlling the p-channel transistors can result in a significant quantization error, as the smallest resistance adjustment which can be made is that achieved by switching on or off the last p-channel transistor, controlled by RBIAS3. Second, once the sequence illustrated in FIG. 2 is complete, the circuit is unable to make any correction in the resistance of the voltage-controlled resistor in the event of a change in temperature or operating condition without repeating the entire adjustment sequence. What is needed is a method which does not suffer from quantization error and also allows for adjustment of the resistance of the voltage-controlled resistor in the event of a change in temperature or operating condition.
The resistor mirror of the present invention includes a feedback control circuit coupled to three or more resistor control output terminals; three or more offset control circuits, each coupled to a resistor control output terminal; a reference voltage-controlled resistor coupled to the resistor control output terminals and to the feedback circuit; and one or more additional voltage-controlled resistors, each coupled to the resistor control output terminals. By means of negative feedback and the described behavior of the offset control circuit, the resistance of the reference voltage-controlled resistor is adjusted to approximate that of a reference resistor or other input device. Coupled to the same resistor control output terminals, the resistance of the additional voltage-controlled resistors will also approximate the resistance of the reference resistor. Through appropriate transistor dimension scaling, the resistance of the one or more additional voltage-controlled resistors may be set to a fixed fraction or multiple of the reference resistor.